make is a command, Makefile is a file (uppercase or lowercase)
Makefile which is a dependency and dependency method
Create a makefile, in Makefile Write:
hello:hello.c Gcc -o hello hello.c / / must start with table
direct make, then ./hello can execute
make hello.c ./hello
Makefile is very important, will Will not Makefile, indicating whether a person has the ability to complete large projects
clear project (clear):
Continue to write in makefile:
hello:hello.c gcc -o hello hello.c clean: rm -f hello
When running by default, from top to bottom, only Generate hello (no clean, clean does not depend on any files)
If you want to use clean, use the make clean command directly.
假目标: Always executed
Pseudo-target is also the target. Why use fake targets?
Because the way to generate (compile) the project is to make directly, clean up directly make clean,
but if you want to compile for the second time, must guarantee to modify the source code.
If you want him to always compile (can be compiled without modification), then we can add .PHONY at the front and is always executed.
Set clean to a pseudo target:
hello:hello.c Gcc -o hello hello.c .PHONY:clean // turns the following tags into pseudo targets Clean: Rm -f hello
can also be set as a pseudo target:
.PHONY:hello Hello:hello.c Gcc -o hello hello.c .PHONY:clean // turns the following tags into pseudo targets Clean: Rm -f hello
So.PHONY is always executed after the definition.
1, make is an instruction. Makefile is a file that puts dependencies.
2, you must start with Tab before relying on the method, and then put the dependency method.
3,.phony defines pseudo targets, which can always be executed