The MAX_FANOUT attribute problem

Fanout, that is, fanout, refers to the number of subordinate modules directly called by the module. If this value is too large, the net performance directly in the FPGA is large, which is not conducive to timing closure. Therefore, you should try to avoid high fanout when writing code. However, in some special cases, due to the need for overall structural design or the inability to modify the code, other optimization methods are needed to solve the problem caused by high fanout. Here are three ways to do this:

First look at the following example, as shown in Figure 1 for the critical path timing report in the transposed FIR filter, which is described in the FIR topic of DSP in FPGA. The fanout of the input FIR filter input data is large. In the figure 1中所示为11,因此net delay高达1.231ns。如图2所示,输入数据驱动了11个DSP48E1。

, in the case of no optimization, the fmax of the design: 206.016MHz

1. Register copy

register copy is to solve the high fanout One of the most common methods of problem is to share the task of driving all modules from the original one by copying several identical registers, and then to achieve the purpose of reducing fanout. By simply modifying the code, as shown in Figure 3, four registers are copied: din_d0, din_d1, din_d2, din_d3, din_d, din_d0, din_d1, din_d2 drive two DSP48E1s respectively, and din_d3 drives three DSP48E1s. In the code to prevent the synthesizer from optimizing the same register, the (* EQUIVALENT_REGISTER_REMOVAL="NO" *) attribute is added to the corresponding signal to avoid optimization. After the

integrated implementation, the timing report is shown in Figure 4. The input data fanout is reduced to 2 on the data path, and the corresponding net delay is also reduced to 0.57 ns. The resulting design is shown in Figure 5. As expected, four registers are copied to share the fanout. After register optimization, get fmax: 252.143MHz

2. max_fanout attribute

can set the signal attribute in the code, set the max_fanout attribute of the corresponding signal to a reasonable value, when the actual design of the signal If fanout exceeds this value, the synthesizer will automatically optimize the signal. The usual method is register copying. The property settings are as follows:

(* max_fanout = "3" *)reg  signed [15:0] din_d;

Set the max_fanout attribute of the din_d signal to 3. After comprehensive implementation, the timing report is shown in Figure 6. The fanout is only 2, and the corresponding net delay is only 0.61ns. The optimization effect is not bad. The structure is shown in Figure 7, where din_d_12_1, din_d_12_2, and din_d_12_3 are automatically added after synthesizer optimization, that is, the register copy function is implemented. After max_fanout attribute optimization, get fmax: 257.135MHz

 3. BUFG

Usually BUFG is a resource for the global clock, which can solve the problem caused by high fanout. However, it is generally used for fan-out or large-scale fan-out signals. The logic involved in such signals is spread throughout the chip, and BUFG can optimize the wiring from a global perspective. Moreover, the BUFG resources in a FPGA chip are also limited, and there are only 32 on the 7k325tffg900. If the high fanout optimization for ordinary signals is not realistic. Therefore, it is necessary to use BUFG on the clock, but if some reset signals are encountered in the design due to timing problems caused by high fanout, BUFG can be used to optimize this signal.